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| ST Sitronix Functions !" #" matrix LCD driver with two 40 channel Dot outputs ST7063C 80CH Segment Driver for Dot Matrix LCD Features !" #" Display driving bias : static to 1/5 #" Power supply for logic : 2.7V ~ 5.5V #" Power supply for LCD voltage (VDD~VEE) : 3V ~ 11V 100 Pin QFP package and bare chip available #" voltage (V1 ~ V4) Bias #" input/output signals !"Input : Serial display data and control pulse from controller IC !"Output : 40 X 2 channels waveform for LCD driving Description !" ST7063C is a segment driver for dot matrix type LCD display. It features 80 channels with 40 X 2 bits bi-directional shift registers, data latches, LCD drivers and logic control circuits. It is fabricated by high voltage CMOS process with low current consumption. The ST7063C can convert serial data received from an LCD controller, such as ST7066U, into parallel data and send out LCD driving waveforms to the LCD panel. The ST7063C is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCD. The LSI can be used as segment driver. The ST7063C has pin function compatibility with the KS0063(B) that allows the user to easily replace it with an ST7063C. V1.3a 1/12 2001/08/29 ST7063C History ST7063C Specification Revision History Version 1.1 1.2 1.2a 1.3 1.3a Date 2000/07/31 First Edition 2000/11/14 Added QFP Pad Configuration(Page 6) 2001/02/26 Changed Application Circuit(Page 11) 2001/05/04 1. 2. ST7063 Transition to ST7063C Moved QFP Package Dimensions Page 12 to Page 5 Description 2001/08/29 Added "Substrate connect to VDD"(Page 4) V1.3a 2/12 2001/08/29 ST7063C Functional Block Diagram !" S1...............................S40 S41...............................S80 V1 V2 V3 V4 SEGMENT DRIVER SEGMENT DRIVER VDD VSS VEE DATA LATCH(40bits) DATA LATCH(40bits) BIDIRECTIONAL SHIFTER(40bits) BIDIRECTIONAL SHIFTER(40bits) M CL1 CL2 CONTOL DL1 SHL1 DR1 DL2 SHL2 DR2 V1.3a 3/12 2001/08/29 78 79 80 81 82 83 84 85 86 87 88 89 90 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 39 38 Size : 3800x2600m Coordinate : center Min. PAD Pitch : 120m Circle here to find the first PAD 37 Pad Arrangement !" 91 92 93 94 95 96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 36 35 34 33 PAD Size : 90x90m "G793E" Marking : Easy to find the PAD 32 ST7063C G793E 31 27 28 29 30 Substrate connect to VDD. V1.3a 4/12 (0,0) 40 2001/08/29 ST7063C Package Dimensions !" V1.3a 5/12 2001/08/29 ST7063C Pin Configuration(QFP 100) !" S 3 1 S 3 2 S 3 3 S 3 4 S 3 5 S 3 6 S 3 7 S 3 8 S 3 9 S 4 0 S 8 0 S 7 9 S 7 8 S 7 7 S 7 6 S 7 5 S 7 4 S 7 3 S 7 2 S 7 1 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 51 V E E V 1 V 2 V 3 V 4 V S S C L 1 S H L 1 S H L 2 N C N C V D D C L 2 D L 1 D R 1 D L 2 D R 2 MN C N C V1.3a 6/12 2001/08/29 ST7063C Pad Name and Coordinates !" Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pad X Y Name Name S42 -1760 -1160 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 -1630 -1160 -1500 -1160 -1380 -1160 -1260 -1160 -1140 -1160 -1020 -1160 -900 -1160 -780 -1160 -660 -1160 -540 -1160 -420 -1160 -300 -1160 -180 -1160 -60 -1160 60 -1160 180 -1160 300 -1160 420 -1160 540 -1160 660 -1160 780 -1160 900 -1160 1020 -1160 1140 -1160 1260 -1160 1380 -1160 1500 -1160 1630 -1160 1760 -1160 1760 -1030 1760 -900 Pad No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pad Name S74 S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 X Y Pad No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pad Name S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 VEE V1 V2 V3 V4 VSS CL1 X Y 1760 -780 1760 -660 1760 -540 1760 -420 1760 -300 1760 -180 1760 -60 1760 60 1760 180 1760 300 1760 420 1760 540 1760 660 1760 780 1760 900 1760 1030 1760 1160 1630 1160 1500 1160 1380 1160 1260 1160 1140 1160 1020 1160 900 1160 780 1160 660 1160 540 1160 420 1160 300 1160 180 1160 60 1160 -60 1160 -180 1160 -300 1160 -420 1160 -540 1160 -660 1160 -780 1160 -900 1160 -1020 1160 -1140 1160 -1260 1160 -1380 1160 -1500 1160 -1630 1160 -1760 1160 -1760 1030 -1760 900 -1760 780 -1760 660 -1760 540 -1760 420 -1760 300 -1760 180 SHL1 -1760 60 SHL2 -1760 -60 VDD CL2 DL1 DR1 DL2 DR2 M S41 -1760 -180 -1760 -300 -1760 -420 -1760 -540 -1760 -660 -1760 -780 -1760 -900 -1760 -1030 V1.3a 7/12 2001/08/29 ST7063C Pin Description !" Pin Name VDD VSS VEE V1 V2 V3 V4 S1-S40 SHL1 Purpose POWER GROUND LCD GND LCD output LCD output segment direction Description for logic for logic for LCD driving voltage used as select voltage level used as non select voltage level LCD driver output for part 1 direction control for part 1 segments If SHL1 = 1 then DL1=out, DR1=in If SHL1 = 0 then DL1=in, DR1=out LCD driver output for part 2 direction control for part 2 segments If SHL2 = 1 then DL2=out, DR2=in If SHL2 = 0 then DL2=in, DR2=out Alternate the LCD driving waveform latch the data after shift is completed shift the data into the segments I/O N/A N/A N/A I I O I DL1, DR1 data in /out I/O S41-S80 SHL2 segment direction O I DL2, DR2 data in/out I/O M CL1 CL2 alternation latch clock shift clock I I I V1.3a 8/12 2001/08/29 ST7063C Functional Description !" Clock The CL1 is the clock to latch data on the falling edge. It latches the data input from the bi-directional shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit of the register to the latch circuit. Shift Registers And Data I/O The ST7063C supplies two sets of 40-bit shift register, which controls the shift direction by SHL1 & SHL2. The SHL1 controls the 1st 40-bit shift register, and SHL2 controls the 2nd 40-bit shift register. When SHL1 is connected to VDD, the 1st shift direction is from S40 to S1; when SHL1 is connected to VSS, the shift direction changes from S1 to S40. When SHL2 is connected to VDD, the 2nd shift direction is from S80 to S41; when SHL2 is connected to VSS, the shift direction changes from S41 to S80. The DL1, DR1, DL2, DR2 are data input or output option function. Shift Direction of Channel 1 SHL1 0 1 Shift Direction S1 $ S40 S40 $ S1 DL1 IN OUT DR1 OUT IN Shift Direction of Channel 2 SHL2 0 1 Shift Direction S41 $ S80 S80 $ S41 DL2 IN OUT DR2 OUT IN V1.3a 9/12 2001/08/29 ST7063C LCD Output Waveforms !" Output of LATCH (DATA) M V2 V4 Output (S1 ~ S80) V3 V1 V1 V2 V4 V3 Timing Characteristics !" TWCKL CL2 VIH VIL TWCKH TR TF TDH TSU Data in (DL1, DL2) (DR1, DR2) TD Data out (DL1, DL2) (DR1, DR2) VOH VOL TSL TLS CL1 TLS TWCKH TR TSU M V1.3a 10/12 2001/08/29 ST7063C D.C Characteristics !" Symbol VDD VLCD VIH VIL ILKG VOH VOL IDD IV Parameter Operating Voltage Driver Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Operating Current Leakage Current Test Condition Min. Typ. Max. Unit Max. VDD-VEE VIN =0 ~ VDD IOH = -0.4mA IOL = +0.4mA FCL2 = 400KHZ VIN =VDD ~ VEE 2.7 3 0.7 VDD 0 -5 VDD -0.4 -10 100 5.5 11 VDD 0.3 VDD 5 0.4 300 10 V V V V uA V V uA uA Applicable pin CL1,CL2,M,SHL1,SHL 2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 V1~V4, S1~S80 VDD,VEE V1 ~ V4 A.C Characteristics !" Symbol FCL TWCKH TWCKL TSL TLS TR/TF TSU TDH TD Parameter Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Clock Set-up Time Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time Test Condition Min. Max. Unit CL2 $ CL1 CL1 $ CL2 CL = 15 PF 800 800 500 500 300 300 400 200 500 KHZ ns ns ns ns ns ns ns ns Applicable pin CL2 CL1,CL2 CL2 CL1,CL2 CL1,CL2 CL1,CL2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 Maximum Absolute Ratings !" Symbol VDD TOPR TSTG Parameters Supply Voltage Operating Temperature Storage Temperature Min. -0.3 -20 -55 Max. 7 75 125 Unit V V1.3a 11/12 2001/08/29 Dot Matrix LCD Panel Application Circuit : (2Line x 40Word) !" Com 1-16 D DL1 VDD SHL1 SHL2 VSS VEE V1 Seg 1-40 Seg 1-80 ST7063C DR2 DL2 DR1 CL1 CL2 M DL1 VDD SHL1 SHL2 VSS VEE V2 V3 V4 V1 Seg 1-80 ST7063C DR2 DL2 DR1 CL1 CL2 M V2 V3 V4 ST7066U VCC GND CL2 CL1 M V1 V2 V3 V4 V5 DB0-DB7 ST7063C Regsister Vcc(+5V) Regsister Regsister Regsister Regsister VR -V or GND Note:Regsister=2.2K~10K ohm VR=10K~30Kohm V1.3a To MPU 12/12 2001/08/29 |
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